1. Field of the Invention
The present invention relates to a MOS semiconductor device and a method of manufacturing a MOS semiconductor device, and more specifically it relates to a semiconductor device that is effective with respect to a non-volatile memory in which current is caused to flow between a gate electrode and a semiconductor substrate, and a method for manufacturing such a semiconductor device.
2. Background of the Invention
A great amount of research is being done with regard to the improvement of the storage capability of storage devices, and flash memories, which are non-volatile memories that, after having been written into, can be electrically erased, have come to gain attention in recent years.
A typical flash memory structure is one which has a floating gate electrode that is electrically insulated.
It is possible to induce an electrical charge into such a floating gate, and to hold this charge as stored data.
When writing or erasing this data, a voltage is applied between the source or the silicon substrate and a second gate electrode, and an electrical charge is either injected into the floating gate electrode or released therefrom.
For this reason, there is a need that the current flowing in the first gate oxide film be uniform over the entire cell array.
However, because of the heat that is applied to the floating gate, when forming the source and drain and when performing reflow of the interlayer insulation film, the crystal grains of the polysilicon grow, so that there is a large amount of n-type or p-type impurities existing at the grain boundary.
For this reason, a huge oxide ridge occurs at the boundary surface between the first gate oxide film and the second gate electrode, which is the floating gate (refer to page 331 of the preprints of IEEE/IRPS: International Reliability Physics Symposium, 1991), so that an excessive erase current flows during erasing when an electric charge is released from the floating gate, this resulting in faulty operation.
This in turn results in a reduction of the production yield of the flash memory.
In a resistive-load device such as an SRAM, a known technology for preventing a drop in the resistance value of the polysilicon of the resistance layer is that of using a three-layer construction in the polysilicon layer, consisting of a polysilicon layer/silicon oxide film layer/polysilicon layer structure (Japanese Unexamined Patent Publication (KOKAI) No. 1-244659).
In the above-noted prior art, let us consider whether or not the growth of the crystal grains in a polysilicon floating gate of a flash memory is prevented by the technology as described in the prior art.
Specifically, the structure is as shown in FIG. 6(B). As shown in FIG. 6(A), the manufacturing method in this case is that of forming a field oxide film 2 onto a p-type silicon substrate so that an element region is divided into islands, and forming a first gate oxide film 3 on a surface of an element region of the silicon substrate 1.
After forming the first gate oxide film 3, the CVD process is used to form a polysilicon film 4 to a thickness of approximately 70 nm, at which point the growth gas is switched to dry oxygen, so that a silicon oxide layer 6 is formed on the surface of the polysilicon film 4 to a thickness of 2 to 5 nm.
The growth gas is restored and a polysilicon layer 7 is formed on the silicon oxide layer 6 to a thickness of approximately 70 nm.
Next, after diffusing an impurity into the polysilicon film 7 to a concentration of, for example, 2.times.10.sup.20 atoms/cc, photolithography and anisotropic etching are used to form the polysilicon film 4, the silicon oxide layer 6, and the polysilicon layer 7 as a three-layer first gate electrode.
Next, as shown in FIG. 6(B), the CVD process is used to deposit a lower-layer second gate oxide film 8 onto the polysilicon film 7 to a thickness of approximately 7 nm, and over this a nitride film 9 is formed to a thickness of approximately 5 nm, an upper-layer second gate oxide film 10 being formed to a thickness of approximately 7 nm on the surface which includes this nitride film 9.
By doing this, the first gate electrode, which is formed by the polysilicon layer 4, the silicon oxide 6, and the polysilicon layer 7 is formed as a floating gate.
Next, a polysilicon film 14 is formed to a thickness of approximately 150 nm as a second gate electrode 11 on the surface that includes the upper-layer second gate oxide film 10.
Then, on this second gate electrode 11, an interlayer insulation film 12 is formed to a thickness of approximately 500 nm, this interlayer insulation film having a contact hole formed in it by means of photolithography and anisotropic etching technologies, thereby forming a metal wire 13. By means of the above-noted process steps, a non-volatile memory is fabricated which has a first and a second gate electrode.
Another know prior art is that which is disclosed in the Japanese Unexamined Patent Publication (KOKAI) No. 6-29540, in which, as shown in FIG. 7, a field oxide film 44 that separates an element region on a p-type silicon substrate into islands is formed on a p-type silicon substrate 41, and a first gate oxide film 43 is formed on the surface of the element region of the silicon substrate 41.
After the first gate oxide film 43 is formed, the CVD process is used to form a polysilicon film 45 to a thickness of approximately 30 to 50 nm, at which point either N.sub.2 annealing is done at a temperature in the range of 700.degree. C. to 800.degree. C., or the structure is left at room temperature for a short period of time, so as to form a silicon oxide film 46 to a thickness of approximately 2 to 3 nm on the surface of the polysilicon film 45.
A polysilicon layer 47 is formed to a thickness of approximately 100 to 150 nm on the surface of the silicon oxide layer 46. Next, after injecting an impurity to concentration of 1 to 8.times.10.sup.14 atoms/cm.sup.2 into this polysilicon layer 47, photolithography and anisotropic etching are used to form the polysilicon film 45, the silicon oxide film 46, and the polysilicon layer 47 as a three-layer first gate electrode.
Next, the CVD process is used to deposit a lower-layer second gate oxide film onto the polysilicon film 47 to a thickness of approximately 7 nm, and over this a nitride film is formed to a thickness of approximately 5 nm, an upper-layer second gate oxide film having a thickness of 7 nm, being formed over the surface which includes this nitride film.
By doing this, the first gate electrode, which is formed by a laminate of a polysilicon layer, a silicon oxide film layer, and a polysilicon layer, is formed as a floating gate.
Next, a polysilicon film is formed to a thickness of approximately 150 nm as a second gate electrode on the surface that includes the upper-layer second gate oxide film.
Then, onto this second gate electrode, an interlayer insulation film is formed to a thickness of approximately 500 nm, this interlayer insulation film having a contact hole formed in it by means of photolithography and anisotropic etching technologies, thereby forming a metal wire.
By means of the above-noted process steps, a non-volatile memory is fabricated which has a first and a second gate electrode.
In the first prior art described above, in a non-volatile MOS memory of the floating gate type, for example, because an impurity such as phosphor is diffused into the polysilicon layer, which is the first gate electrode, as is clear as well from the cited literature, the thermal processing for forming the diffusion layer and thermal processing for reflow of the interlayer insulation film in the process of fabricating the floating gate type non-volatile MOS memory diffuse the impurity via the crystal grains and reach the first gate oxide film.
Therefore, in the region of the crystal grains of the first gate oxide film, the impurity diffuses through the oxide film, causing a buildup of the first gate oxide film, the diffusion film enters into the first gate electrode, and the phenomenon of phosphor or other n-type impurity diffusing into the oxide film (oxide ridge formation) occurs.
Because of this phenomenon, when an electric charge is injected into or extracted from the floating gate of a floating gate non-volatile MOS memory of an electric charge, an excessive erase current occurs. This can cause faulty operation and a reduction in the production yield of floating gate type non-volatile MOS memories.
In the second example of prior art described above, in the case in which a floating gate type non-volatile MOS memory is fabricated using the technique of forming a three-layer structure of polysilicon layer/silicon oxide film/polysilicon layer as the polysilicon layer 48, it is possible to inhibit crystal grain growth, and it is possible to achieve a uniformly occurring oxide ridge and to somewhat reduce the failures related to excessive erasing.
However, because the purpose of the above-noted prior art is to prevent a reduction in the resistance value of the polysilicon, it has a feature the formation of a silicon oxide layer in the center part of the polysilicon layer.
For this reason, this prior art's effectiveness of inhibiting the occurrence of an oxide ridge at the boundary between the first gate oxide film and the first gate electrode by inhibiting crystal grain growth is small, and cannot be expected to achieve a great reduction in the excessive erase current.
According to this prior art, there does exist the possibility that, in the case of using a three-layer floating gate structure of polysilicon layer/silicon oxide film/polysilicon layer, there will be an inhibition of the growth of crystal grains and a reduction in excessive erase current.
However, as the density of flash memories increase, at 16 Mbits and beyond, it become necessary to have polysilicon with a crystal grain size of 50 nm or smaller (refer to page 847, IEEE/IEDM '94 Technical Digest, 1994).
Because in the second cited example of prior art the growth of the lower-layer of the floating gate is polysilicon growth, even if control is performed of the thermal processing and amount of impurities, the grain size will be 50 nm or larger.
Thus, the inhibition of an excessive erase current in the second cited prior art will not achieve a great effect of improvement for levels of integration of flash memories of 16 Mbits or greater.
Accordingly, an object of the present invention is to achieve an improvement with respect to the drawbacks of the prior art as cited above, by providing a semiconductor device having a gate electrode that is formed by a polysilicon layer having a crystal grain size of no greater than 50 nm, and in particular a flash memory having such as gate electrode which, at a level of integration of 16 Mbits or greater, provides a reduction in the frequency of occurrence of excessive erasing failures, and a method of manufacturing the above-noted semiconductor device.